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Aurora Documentation: Difference between revisions
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[https://www.hotchips.org/hc30/2conf/2.14_NEC_vector_NEC_SXAurora_TSUBASA_HotChips30_finalb.pdf Hot Chips 2018 Aurora TSUBASA Architecture, contains details about caches and memory design] | [https://www.hotchips.org/hc30/2conf/2.14_NEC_vector_NEC_SXAurora_TSUBASA_HotChips30_finalb.pdf Hot Chips 2018 Aurora TSUBASA Architecture, contains details about caches and memory design] | ||
[https://sxauroratsubasa.sakura.ne.jp/documents/veos/en/VEOS_high_level_design.pdf VEOS High Level Design Overview] | |||
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Latest revision as of 16:36, 8 December 2022
Manuals and Introductions
Landing page for all manuals, Compilers, Tools and Libraries of the SDK
Getting started with compilers, Slides for Fortran and C++ Compiler, with Tuning
Vectorization Training, self guided material
global online discussion forum about Aurora TSUBASA
Advanced Material
VE offloaind, running programm on VH and offloading parts to VE
blog about VE usage/tools/LLVM/offloading/HPCG performance
blog about aurora in deep learning/Tensorflow/LLVM
frovedis, Spark like API for data analytics
wikichip article on Aurora TSUBASA architecture
Presentations
History of vector computers leading to SX aurora TSUBASA
Hot Chips 2018 Aurora TSUBASA Architecture, contains details about caches and memory design