- Infos im HLRS Wiki sind nicht rechtsverbindlich und ohne Gewähr -
- Information contained in the HLRS Wiki is not legally binding and HLRS is not responsible for any damages that might result from its use -
NEC SX-9 Overview: Difference between revisions
m (→frontends) |
m (Hpcbern moved page Overview to NEC SX-9 Overview: "Overview" is too unspecific) |
(No difference)
| |
Latest revision as of 00:01, 29 September 2023
compute nodes
The HLRS SX-9 installation consists of 8 nodes SX-9 with
- 16 CPUs each node
- 512GB memory per node
The CPUs main features are
- 8 pipesets (SX-8 had 4)
- 3.2 Ghz clock (vector unit)
- 2 add and 2 multiply per pipeset (SX-8 had 2)
- 102.4 gflops peak performance
- 256 GB/sec memory bandwidth per CPU
The 8 nodes are interconnected using an IXS switch, each node has a peak transfer performance of 32GB/s both directions.
The nodes connect to the filesystems with 4x2gbit FC channels.
frontends
the frontends which are used as access gateways, for crosscompiling and for interaction with batch system are 2 NEC Express5800 140-rf4, each having 4 2.93 ghz quadcore Intel Xeon CPUs and 128 GB of RAM.
They connect to the filesystem with 4x2Gbit FC channels each.
They (will have) fast 10Gbit connections to the outside and towards HPSS storage system.