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Aurora Documentation: Difference between revisions
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[https://www.hotchips.org/hc30/2conf/2.14_NEC_vector_NEC_SXAurora_TSUBASA_HotChips30_finalb.pdf Hot Chips 2018 Aurora TSUBASA Architecture, contains details about caches and memory design] | [https://www.hotchips.org/hc30/2conf/2.14_NEC_vector_NEC_SXAurora_TSUBASA_HotChips30_finalb.pdf Hot Chips 2018 Aurora TSUBASA Architecture, contains details about caches and memory design] | ||
[https://doc.itc.rwth-aachen.de/download/attachments | [https://doc.itc.rwth-aachen.de/download/attachments/44466567/Aurora_VE_Intro_ML.pdf AI on aurora] | ||
Revision as of 18:30, 8 February 2020
Getting started with compilers, Slides for Fortran and C++ Compiler, with Tuning
online training material from NEC Germany for workshops, feasable for self study
Tuning Guide, overview about vectorization and tuning
global online discussion forum about Aurora TSUBASA
Advanced Material
VE offloaind, running programm on VH and offloading parts to VE
blog about VE usage/tools/LLVM/offloading/HPCG performance
blog about aurora in deep learning/Tensorflow/LLVM
Presentations
History of vector computers leading to SX aurora TSUBASA
Hot Chips 2018 Aurora TSUBASA Architecture, contains details about caches and memory design