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Difference between revisions of "Overview"

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* 8 pipesets (SX-8 had 4)
 
* 8 pipesets (SX-8 had 4)
 
* 3.2 Ghz clock
 
* 3.2 Ghz clock
* 2 add and 2 multiply per pipeset
+
* 2 add and 2 multiply per pipeset (SX-8 had 2)
 
* 102.4 gflops peak performance
 
* 102.4 gflops peak performance
* 256 gbyte/sec memory bandwidth
+
* 256 GB/sec memory bandwidth per CPU
  
 
The 8 nodes are interconnected using an IXS switch,
 
The 8 nodes are interconnected using an IXS switch,
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both directions.
 
both directions.
  
The nodes connect to the filesystems with 4 2gbit FC channels.
+
The nodes connect to the filesystems with 4x2gbit FC channels.
  
 
== frontends ==
 
== frontends ==
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the frontends which are used as access gateways, for crosscompiling
 
the frontends which are used as access gateways, for crosscompiling
 
and for interaction with batch system are 2 NEC Express5800 140-rf4,
 
and for interaction with batch system are 2 NEC Express5800 140-rf4,
each having 4 2.93 ghz quadcore intel xeon CPUs and 18 GB of RAM.
+
each having 4 2.93 ghz quadcore intel xeon CPUs and 128 GB of RAM.

Revision as of 16:24, 28 November 2008

compute nodes

The HLRS SX-9 installation consists of 8 nodes SX-9 with

  • 16 CPUs each node
  • 512GB memory per node

The CPUs main features are

  • 8 pipesets (SX-8 had 4)
  • 3.2 Ghz clock
  • 2 add and 2 multiply per pipeset (SX-8 had 2)
  • 102.4 gflops peak performance
  • 256 GB/sec memory bandwidth per CPU

The 8 nodes are interconnected using an IXS switch, each node has a peak transfer performance of 32GB/s both directions.

The nodes connect to the filesystems with 4x2gbit FC channels.

frontends

the frontends which are used as access gateways, for crosscompiling and for interaction with batch system are 2 NEC Express5800 140-rf4, each having 4 2.93 ghz quadcore intel xeon CPUs and 128 GB of RAM.