HPE Hawk

For the Hawk installation schedule please see [Hawk installation schedule].

If your job does not start, please have in mind the time-dependent limitations according to Batch System!

This Page is under construction!

The information below applies to the Test and Development System (TDS) which is similar to the future Hawk production system. Please have in mind that this is a system under construction. Hence modifications might occur without announcement and stuff may not work as expected from time to time!

Hardware

Node/Processor

Compute nodes as well as login nodes are equipped with

 AMD EPYC 7702 64-Core Processor

detailed information will be provided later. Please check for additional infos AMD Rome 7702 With respect to node and processor details cf. here.

Interconnect

Hawk deploys an Infiniband HDR based interconnect with a 9-dimensional enhanced hypercube topology. Please refer to here with respect to the latter. Infiniband HDR has a bandwidth of 200 Gbit/s and a MPI latency of ~1.3us per link. The full bandwidth of 200 Gbit/s can be used if communicating between the 16 nodes connected to the same node of the hypercube (cf. here). Within the hypercube, the higher the dimension, the less bandwidth is available. Topology aware scheduling is used to exclude major performance fluctuations. This means that larger jobs can only be requested with defined node numbers (64, 128, 256, 512, 1024, 2048 and 4096) in regular operation. This restriction ensures optimal system utilization while simultaneously exploiting the network topology. Jobs with a node number of < 128 nodes are processed in a special partition. Jobs over 4096 nodes are processed at special times.

Access

Login-Node: hawk-tds-login1.hww.hlrs.de

Note: Access to the Hawk TDS is possible now on request. In case you have early access, we ask you to provide us with your experience regarding usage and performance (approximately half a page) once a month.

Module environment

cf. here

Compiler

cf. here

MPI

Tuned MPI: In order to use the MPI implementation provided by HPE, please load the Message Passing Toolkit (MPT) module mpt (not ABI-compatible to other MPI implementations) or hmpt (ABI-compatible to MPICH-derivatives).

User Guide: For detailed information cf. the HPE Message Passing Interface (MPI) User Guide.

Performance optimization: With respect to MPI performance optimization by means of tuning environment variables please cf. Tuning of MPT

Libraries

cf. here

Batch System

cf. here

Disk storage

Home directories as well as workspaces are handled in the same way as on Hazel Hen, so please cf. Storage Description regarding details.

Manuals

Processor:

• Software Optimization Guide for AMD EPYC Rome Processors
• Open-Source Register Reference for AMD EPYC Rome Processors
  (in particular describing available hardware performance counters)
• Software Optimization Guide for AMD Family 15h
  (although depicting an older family of AMD processors, the optimization approaches shown in this document are also applicable to the AMD EPYC Rome processor deployed in Hawk)

MPI:

• HPE Message Passing Interface (MPI) User Guide

Batch system:

• User's Guide
• Reference Guide (cf. this with respect to a complete list of environment variables exported by PBS)